Can we use discrete latches and AND/OR gates instead of ICG?

In the post, Integated Clock Gating Cell, we discussed that an ICG has a negative level-sensitive latch preceding an AND gate in order to relax hold timing for clock gating check. And we discussed that it gives benefits for area, power and timing. Let us discuss how area, power and timing are saved. We will discuss only for the case of AND gate, the same will follow for OR gate.

1. Architectural benefits - simplicity in clock handling: By introducing ICGs in place of discrete gates, you dont have to worry about the launch edge of the signal while writing RTL (for details, see here). One can always launch the signal from positive edge-triggered flip-flop for timing and architectural simplicity without worrying about possibility of glitch in clock path due to wrong polarity flip-flop launching enable signal.

2. Benefits in area and power: Having custom module allows for better utilization of resources inside the custom ICG module; hence, it is expected to have lesser power than a latch and an AND gate combined.

3. Benefits in timing: Having the path from latch -> AND inside ICG saves us from having to meet these paths individually, which could take a lot of effort with discrete latch and AND gate. Also, it allows for latch to have almost full time borrow, thereby making almost a full cycle path from a positive edge-triggered flip-flop to ICG.

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Clock gating cell

Clock gating is a very common technique to save power by stopping the clock to a module when the module is not operating. As discussed in Clock switching and clock gating checks, there are two kinds of clock gating checks at combinational gates. We also discussed that for an AND type check, enable must launch from a negative edge-triggered flip-flop and for an OR type check, enable must launch from a positive edge-triggered flip-flop. However, it is very difficult to control the generic state machine to launch the signals to gate a clock either all from positive edge or from negative edge.

Evolution of integrated clock gating cell: To reduce the burden of same kind of launch registers from the state machine, an AND type clock gate can always be preceded with a negative level-sensitive latch and an OR type clock gate can be preceded with a positive level-sensitive latch. This has the same impact as a lockup latch in case of scan chain and eases hold timing. It results in zero cycle hold check from both positive and negative edge-triggered registers, without introduction of any additional latency. Since, each clock gate has to be preceded by a latch, why not build a special cell with an AND gate + a negative level-sensitive latch (or an OR gate + a positive level-sensitive latch). This concept served as motivation for Integrated Clock Gating Cell. This will provide more optimum area, power and timing for the resulting structure.

Test enable pin in integrated clock gating cell: During shift in scan testing, all the clock control signals have to be bypassed to let shifting happen. This can be achieved by providing a bypass signal called “test enable” that is ORed with functional enable signal (shown in figure 1 below). As soon as design goes into shift mode, test enable signal goes high, thereby bypassing all functional enable signals. So, it makes sense to embed this OR gate into integrated clock gating cell itself.

Structure of integrated clock gating cell: Figure 1 below shows the structure of the two kinds of integrated clock gating cells. The one on the left has an AND gate preceded by a negative level-sensitive latch. The enable and test_enable are active high. Clock_out has an inactive low state. The one on the right is complementary to this. It has an OR gate preceded by a positive level-sensitive latch. Both enable and test_enable are active high and output clock has an inactive high state. In case enable and test_enable are active low, NOR gate should be replaced by AND gate.

Figure 1: (a) AND type integrated clock gating cell                         Figure 1: (b) OR type integrated clock gating cell

Hope you’ve found this post useful. Let us know what you think in the comments.

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• Clock gating interview questions